1. Field of the Invention
This invention is related to the field of driver and receiver circuits on an integrated circuit, wherein the driver and receiver circuits are capable of receiving and driving a higher voltage than the voltage supplying the integrated circuit core. The driver circuit includes programmable pullup and pulldown transistors capable of driving a voltage higher than the voltage supplying the integrated circuit core or, in the alternative, driving a voltage substantially equal to the voltage supplying the integrated circuit core.
2. Description of the Relevant Art
Integrated circuits are used in a wide variety of applications including computer systems, personal information devices such as cellular phones and electronic organizers, and automobile electronic control systems. As used herein, the term "integrated circuit" refers to any electronic device which embodies a predetermined set of functions upon a single monolithic substrate.
Integrated circuits may be fabricated in different semiconductor technologies. The selection of a particular semiconductor technology with which to fabricate a particular integrated circuit depends on many factors. The semiconductor technologies available when designing the particular integrated circuit in many ways dictate how the circuit will perform. The cost involved in fabricating the integrated circuit also determines circuit operability given the limited resources in many wafer fabrication sites. Considerations related to the application for which the integrated circuit is designed, such as operable temperature ranges and power consumption constraints imposed by circuit application may also affect the choice of semiconductor technology.
Complimentary metal-oxide-semiconductor (CMOS) technology is a particularly popular semiconductor technology for many applications. Two types of transistors may be formed in a CMOS process: PMOS transistors and NMOS transistors. PMOS transistors and NMOS transistors have four terminals (or connection points): a gate terminal, a source terminal, a drain terminal, and a bulk terminal. Electric current flows from the source terminal to the drain terminal of a transistor when a voltage applied to the gate terminal has either a higher or lower value than the voltage applied to the source terminal, depending on the transistor type. A PMOS transistor is a transistor in which current flows if the voltage applied to the gate terminal is lower than the voltage applied to the source terminal. An NMOS transistor is a transistor in which current flows if the voltage applied to the gate terminal is higher than the voltage applied to the source terminal. The bulk terminal is connected either to the source terminal or to a proper bias voltage.
In both the PMOS transistor and NMOS transistor, the difference in voltage between the gate terminal and the source terminal must be larger in absolute value than a certain voltage before current flow begins. This certain voltage is referred to as a "threshold" voltage and is the voltage required to form an energized channel between the source and the drain diffusion regions in the PMOS transistor or NMOS transistor. As will be appreciated by those skilled in the art, a transistor is formed on a substrate by diffusing impurities into two regions (a drain diffusion region and a source diffusion region). The two regions are separated by a distance of undiffused substrate material called a channel, over which the gate terminal is constructed. By applying a voltage to the gate terminal of the transistor, the channel is energized such that current may flow between the source diffusion region and the drain diffusion region.
A particular CMOS semiconductor technology requires a relatively narrow range of power supply voltages to operate properly. If a power supply voltage lower than the specified range is used, transistors may not be capable of developing voltage levels large enough to cause significant current flow through the transistors. If a power supply voltage higher than the specified range is used, many problems may occur. Among such problems are "hot carrier effects" which may cause damage to transistors. Carriers are electrons or holes which flow through the channel region of a transistor when it is energized via a voltage difference between the gate terminal and the source terminal of the transistor. Hot carrier effects may be generated in two ways. First, substrate hot carriers are generated as a result of large voltage differences between the gate terminal and the bulk terminal of a transistor. Carriers are generated in the bulk and accelerate across the channel. If the voltage difference is large enough, the carriers may inject into the oxide layer between the gate conductor and the silicon surface. Second, channel hot carriers originate from channel current and impact ionization current near the drain junction. Carriers may gain sufficient energy to inject into the aforementioned oxide. Carriers embedded in the oxide cause the threshold voltage of the transistor to shift, reducing current capability of the transistor. Another problem associated with voltages higher than the specified range is oxide breakdown. When oxide breakdown occurs, an electrical short is created between the gate terminal and the source terminal, the drain terminal, or the channel.
Modern integrated circuits are being fabricated in CMOS semiconductor technologies having power supply voltage ranges lower than previously developed CMOS semiconductor technologies. Voltage ranges are decreasing due to the shrinkage of transistor geometries as CMOS semiconductor technologies improve. Shrinking geometries allow more transistors to be placed within a given area of a semiconductor substrate. Thus, more functionality may be included within a particular area of substrate used to manufacture an integrated circuit. As transistor geometries shrink, the voltage that the transistors are capable of withstanding decreases as well. For example, a shorter channel and a thinner oxide imply that a lower voltage applied across the gate oxide may induce hot carrier effects and cause oxide breakdown.
Modern integrated circuits are required to interface to older integrated circuits in many applications. For example, computer systems use a mix of integrated circuits implemented in different semiconductor technologies. Some of these integrated circuits require a nominal power supply voltage of 5.0 volts. Other integrated circuits are fabricated in semiconductor technologies requiring a nominal power supply voltage of 3.3 volts. A "nominal" power supply voltage is the power supply voltage at which the transistors embodied in the particular semiconductor technology provide optimal performance and reliability. Typically, the actual power supply may vary higher or lower than the nominal value by some percentage defined by the semiconductor manufacturer. A 5% to 10% variation from the nominal value is typically allowed. Therefore, a maximum allowable voltage level can be defined with respect to a particular semiconductor technology. The maximum allowable voltage is slightly above the allowable variation from the nominal power supply value.
A particularly difficult problem with interfacing integrated circuits requiring dissimilar nominal power supply voltages is handling the higher voltages that the 5.0 volt integrated circuits produce on interface buses to which 3.3 volt integrated circuits are connected. Typically, CMOS integrated circuits produce voltages on their output pins which are substantially equal to the power supply voltage if the pin is conveying a logical one value. Therefore, 5.0 volt integrated circuits may drive a 5.0 volt signal onto an interface bus. A 5.0 volt signal connected directly to an integrated circuit with a nominal power supply voltage of 3.3 volts would cause hot carrier effects and/or oxide breakdown to occur in the receiving integrated circuit. It would be advantageous for integrated circuits with a 3.3 volt power supply to be able to receive 5.0 volt input signals and drive 5.0 volt output signals without sustaining damage to the integrated circuit.
A 3.3 volt operable integrated circuit with 5.0 volt input/output capabilities could be of even further benefit if it could achieve selectable power conservation. Such an integrated circuit conserves power if it is capable of driving output signals at 3.3 volts when employed in an application not utilizing 5.0 volt integrated circuits. Accordingly, an advantage is gained by having an integrated circuit, if called upon, can receive and output 5.0 volt signals; however, if not called upon, the integrated circuit will receive and output 3.3 volt signals. Such an integrated circuit would be useful as an interface circuit which can programmably select its input and output voltage levels to achieve optimal power usage.
It would be desirable for such an integrated circuit to be programmably configurable, for example, via a programmable pullup and pulldown function to pull up or pull down interface buses when they are not in use. The pullup function would charge the conductors of a bus to the power supply voltage level (e.g. 3.3 volts or 5.0 volts). The pulldown function would discharge the conductors of a bus to the ground voltage level. The desired pullup or pulldown features would serve to conserve power in applications where the bus is idle for long periods of time. Taking advantage of CMOS principles whereby CMOS circuits consume minimal power when their inputs are at power supply or ground voltage levels, the desired integrated circuit must include programmed units which provide power and ground voltages at CMOS inputs via pullup and pulldown functions. The desired pullup and pulldown functions would be resistive, such that the pullup or pulldown functions consume little power during the drive phase.